1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly, relates to a method of fabricating a gate stack of a semiconductor device.
2. Description of the Related Art
In recent years, semiconductor device fabricating technology has continually sought new ways to achieve high device performance, low cost, and great device densities. For example, in the case of a dynamic random access memory (DRAM), high device densities can be used for forming trench capacitor structures during DRAM fabrication. Additionally, while reducing device critical dimension (CD), word line (WL) or so-called gate conductor (GC) stacks of DRAM cells will also be shrunk.
Nevertheless, for conventional WL etching processes, precision is limited due to the uneven topography of the laminate layers for subsequent WL etching given the differentiated step height of the underlying shallow trench isolations (STI). Specifically, WL etched on uneven topography results in bridge problems with WL to WL shorting due to under-etching and device leakage and failure problems with WL punch through due to over-etching. As a result, the conventional WL etching processes increases device defect density and unreliability.
Thus, a novel and reliable method of fabricating a gate stack of a semiconductor device for reducing WL to WL short and device leakage is needed.